(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process sequence used to form sidewall spacers, and salicide blocking shapes, using silicon nitride.
(2) Description of Prior Art
The use of complimentary metal oxide semiconductor, (CMOS), devices, for both logic, as well as memory applications, fabricated on the same semiconductor chip, have resulted in increased process complexity, as well as increased cost, for the integrated CMOS devices. The ability to share specific process steps, or sequences, used for each type, logic and memory, can significantly reduce process complexity and cost. For example a Self-ALigned metal silICIDE, (salicide), layer, is used with the high performance, CMOS logic devices, while the salicide layer is not desired for CMOS memory applications. A silicon nitride shape is sometimes used to block salicde formation in the CMOS memory region, while being introduced in the CMOS logic area. The silicon nitride layer used for the salicide blocking shape, can however be the second silicon nitride used in the integration of CMOS logic and memory devices. Prior to formation of heavily doped source/drain regions, for both type devices, sidewall spacers, formed from a first silicon nitride layer, are formed on the sides of gate structures, to prevent gate to substrate leakage or shorts. Since the integrity of the sidewall spacer, as well as the quality of the silicide blocking shape, are paramount, high quality silicon nitride layers, in terms of diffusion barrier, are needed for these functions. Therefore these silicon nitride layers are obtained via a low pressure chemical vapor deposition, (LPCVD), procedure, usually performed at a temperature between about 800 to 900.degree. C., instead of the use of plasma enhanced vapor deposition, (PECVD), silicon nitride layers, obtained at temperatures lower than 800.degree. C.
The use of two, high temperature deposited silicon nitride layers, however can exhaust the thermal budget allotted for the fabrication of the integrated CMOS chip,. in terms of unwanted movement of doping profiles. Therefore a novel process sequence, utilizing only a single silicon nitride layer, for both sidewall spacer, and salicide blocking shape, will be presented, removing one high temperature process, thus preserving the thermal budget. The novel process sequence detailed in this present invention, features definition of a silicon nitride blocking shape, in the CMOS memory region, and the formation of a L shaped, silicon nitride spacer, on the sides of CMOS logic gate structures, with both silicon nitride shapes defined from the same LPCVD silicon nitride layer. Salicide formation is then initiated in the CMOS logic region, while the silicon nitride blocking shape protects all CMOS memory regions, during the salicide procedure. Prior art, such as Cote et al, in U.S. Pat. No. 4,838,991, as well as Chor et al, in U.S. Pat. No. 5,801,077, describe the use of organic spacers, on the sides of gate structures, however these prior arts do not describe the process sequence for forming silicon nitride, sidewall spacers, for both memory and logic devices, and a salicide blocking shape, for memory devices, from a single deposition of an LPCVD silicon nitride layer.